Atmel’s AT94K and AT94S family of Field Programmable System Level Integrated Circuits (FPSLIC devices) combine all the basic system building blocks (logic, memory and uC) in an SRAM-based monolithic field programmable device. The FPSLIC programmable SLI platform allows true system level designs to be implemented without the need for expensive NRE (non-recurring engineering) charges or costly software tools. FPSLIC for the first time puts system level integration on every designer’s desk.
The FPSLIC Secure (AT94S) family of devices offers security and even higher integration. In addition to the FPGA, AVR and SRAM memory these devices have an on-chip serial configuration memory. The combination of FPSLIC and the serial configuration memory in a single package allows for ISP and remote updates of FPSLIC while hiding programming code for the FPGA and AVR micro.
FPSLIC devices combine 5K to 40K gates of Atmel’s patented AT40K FPGA architecture, a 20 MIPS AVR 8-bit RISC microprocessor core, numerous fixed microcontroller peripherals and up to 36 Kbytes of program and data SRAM.
The AT17LV256, AT17LV512 and AT17LV010 are EEPROM Configuration Memories that provide an easy-to-use, cost-effective configuration memory for programming Field Programmable System Level Integrated Circuits (FPSLICs) by using a simple serial-access procedure to configure one or more FPSLIC devices. Its small form factor allows designers to save board space and offers the possibility of using spare memory to store system parameters from the FPSLIC.
The FPSLIC design software (System Designer™) is based on industry standard FPGA and microcontroller design tools. The System Designer environment from Atmel includes modified version of the mature FPGA development tools and the AVR studio tools. Version 3.1 is now shipping..
- Eliminates Prototype Boards by allowing the microcode and the hardware design to be developed simultaneously without a prototype board.
- Allows Hardware/software Trade-off to quickly explore and test various hardware/software implementations to arrive at a highly optimized design.
- Faster Design Cycles by allowing the concurrent design of hardware and software. Parallel Hardware/Software Development by removing the software from the critical path and reducing Design cycle time.
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