Category: FPGA

All about Field Programmable Gate Array, Verilog and VHDL

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FPGA Mikrokontroler

USB On-The-Go: Pendahuluan

Pernahkah Anda bayangkan menghubungkan antara satu HP dengan HP lain baik dari merek atau tipe yang sama atau berbeda sama sekali? Bukan melalui bluetooth? Atau ingin mencetak foto dari HP langsung ke printer tanpa melalui PC atau bleutooth? Atau antara kamera digital dengan printer digital?

Saat ini sudah banyak pengguna yang cenderung memiliki keinginan atau kebutuhan untuk menghubungkan piranti-piranti bergerak (mobile devices) dengan periferal-periferal mereka. Hal ini dilakukan dengan berbagai cara atau metode termasuk penggunaan dock, dongle, slot-slot, konektor-konektor khusus dan 7 macam teknologi kartu (card technologies) yang ada saat ini. Tentu saja cara-cara tersebut menjadi sangat ribet dan rumit jika sudah melibatkan beberapa piranti sekaligus. Untuk mengatasi hal tesebut, beberapa produsen HP (mobile phone) dan PDA telah bekerja-sama untuk mengembangkan sebuah standar teknologi yang berbasis pada spesifikasi USB yang sudah populer yang kemudian dimodifikasi khusus untuk aplikasi-aplikasi mobile. Hasilnya berupa USB On-The-Go (OTG).

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FPGA

CMP vs. CMT, what’s this?

The techniques being embraced across the microprocessor industry are chip multiprocessors (CMPs) and chip multithreaded (CMT) processors. CMP, as the name implies, is simply a group of processors integrated onto the same chip. The individual processors typically have comparable performance to their single-core brethren, but for workloads with sufficient thread-level parallelism (TLP), the aggregate performance delivered by the processor can be many times that delivered by a single-core processor. Most current processors adopt this approach and simply involve the replication of existing single-processor processor cores on a single die.

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FPGA

OpenSPARC Training (8-9 Juni 2009)

OpenSPARC is an open source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems‘ Register transfer level (RTL) Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On 21 March 2006, Sun released the source code to the T1 IP core under the GNU General Public License. On December 11, 2007, Sun also made the UltraSPARC T2 processor’s RTL available via the OpenSPARC project.

Selama dua hari, 8 dan 9 Juni 2009, Kelompok Keahlian Elektronika, STEI-ITB mengadakan OpenSPARC Training yang langsung diisi oleh David L. Weaver (editor buku OpenSPARC Internal, unduh bukunya disini). Untuk acara ini Komunitas OpenSPARC-UGM yang diwakili oleh Agfianto E.P. mengadakan video conference (vicon) langsung di Ruang Sidang PPTIK, UGM.

pak Trio Adiono, Ph.D. sedang memberikan sambutan

Acara dimulai dengan pembukaan oleh pak Trio Adiono (KK Elektronika, yang punya acara), pak Adang Suwandi (Dekan STEI), dan pak Harry Kaligis (Sun Microsystems). Setelah itu acara langsung dimulai dengan presentasi oleh David Weaver, Chief OpenSPARC Evangelist dari Sun Microsystems. Informasi tentang Workshop ini juga bisa Anda baca di blog-nya pak Budi Rahardjo (klik donk).

David Weaver memberikan presentasi latar belakang OpenSPARC

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FPGA Mikrokontroler

Indonesia OpenSPARC Iniative Workshop

Pada hari Rabu, 25 Maret 2009, ITB mengundang tiga perguruan tinggi, UGM, ITS dan UI, untuk bersama-sama mendiskusikan berbagai macam kemungkinan proyek yang mendapat dukungan dari Sun Microsystem dengan program OpnSPARC-nya. Kebetulan dari UGM saya (Agfianto Eko Putra, M.Si. dan Alrosyid, S.Si. yang menggantikan Jazi Eko Istiyanto, Ph.D. yang sedang ke Belanda saat itu) yang mewakili (asli dari ELINS, Elektronika dan Instrumentasi, Jurusan Fisika, Fak. MIPA, UGM – Yogyakarta). Ini merupakan pertemuan awal, dan semoga akan terus berlangsung dengan pertemuan-pertemuan lainnya yang dikoordinasi ITB (melalui pak Trio Adhiono, Ph.D.) untuk memajukan riset dan industri semikonduktor di Indonesia, khususnya industri mikroprosesor.

Pertemuan yang juga dihadiri oleh Dekan STEI, ITB dan Vice President of Sun Microsystems Asia Pacific Region diawali dengan diskusi atau brainstorming beberapa kemungkinan topik-topik yang bisa dikerjakan bersama dan setiap perguruan tinggi yang terlibat (ITB, UGM, UI dan ITS).

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FPGA Mikrokontroler

FPSLIC™ (AVR with FPGA)

Atmel’s AT94K and AT94S family of Field Programmable System Level Integrated Circuits (FPSLIC devices) combine all the basic system building blocks (logic, memory and uC) in an SRAM-based monolithic field programmable device. The FPSLIC programmable SLI platform allows true system level designs to be implemented without the need for expensive NRE (non-recurring engineering) charges or costly software tools. FPSLIC for the first time puts system level integration on every designer’s desk.

The FPSLIC Secure (AT94S) family of devices offers security and even higher integration. In addition to the FPGA, AVR and SRAM memory these devices have an on-chip serial configuration memory. The combination of FPSLIC and the serial configuration memory in a single package allows for ISP and remote updates of FPSLIC while hiding programming code for the FPGA and AVR micro.

FPSLIC devices combine 5K to 40K gates of Atmel’s patented AT40K FPGA architecture, a 20 MIPS AVR 8-bit RISC microprocessor core, numerous fixed microcontroller peripherals and up to 36 Kbytes of program and data SRAM.

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FPGA

Sony Playstation Prototyping with LabVIEW, Xilinx FPGA

Engineers designed serial protocol for Sony Playstation 2 controller using NI PXI R Series reconfigurable I/O hardware with Xilinx Virtex-5 FPGA programmed with NI LabVIEW FPGA. As a result, they were able to iterate on design by prototyping with LabVIEW, high-performance PXI and reconfigurable FPGA.

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FPGA

FPGA Basics by Vineet

Vineet describes what FPGAs are and how they are useful…

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FPGA

Simulasi Lampu Trafik!

Simulasi lampu trafik menggunakan LogiFlash bisa Anda coba saksikan sendiri dengan mengklik gambar di bawah ini (maaf keterangan dalam Bahasa Jerman)…

Anda bisa menggunakan LogiFlash untuk belajar elektronika digital, silahkan klik pada Links di sebelah kanan bagian “Belajar Elektronika Digital” atau klik disini, selamat mencoba.

Tutorialnya kapan-kapan saya tulis… mohon dukungan, terima kasih!

Ada pertanyaan? Komentar? silahkan…

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FPGA

Floating-point Unit Implementation in Altera FLEX10K FPGA using VHDL

Floating-point systems were developed to provide high resolution over a large dynamic range. Floating-point systems can often provide a solution when fixed-point systems, with their limited dynamic range, fail. Floating-point systems, however, bring a speed and complexity penalty. Most microprocessor floating-point systems comply with the published single- or double-precision IEEE floating-point standard; while in FPGA-based systems often employ custom formats. In this research, a 16-bit floating-point unit, which has addition, subtraction, multiplication and division operator, and based on floating-point system, has been implemented in Altera FLEX10K FPGA using VHDL (VHSIC Hardware Description Language). The design used structural and behavior model implementation to know which the best design is. The best results are structural model using ROM which require 438 logic elements with 7.99 MFLOPS (million floating-point operations per second), and the behavior model using ROM which require 526 logic elements with 7.51 MFLOPS. The floating-point unit has been designed for normal floating-point operation, thus it can not detect overflow or underflow conditions.

Download full paper here (PDF) – The 1st International Seminar on Sciences and Technology (ISSTEC) 2009.

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FPGA

Images and High-Speed Processing using FPGAs

This application is designed to show how several high data rate applications can be handled using VHDL on FPGAs (Field Programmable Gate Arrays). The system consists of a high speed camera, processor core, disk drive interface, Random Access Memory (RAM) interface and serial link to an external Program Counter (PC). The overall system has been chosen to illustrate how to move large amounts of data around quickly and efficiently. The outline of such a test application is shown in the figure below. As can be seen, there are several key aspects involved, but mainly it is about moving large amounts of data around a system quickly, efficiently and reliably.

The basic system is shown in outline form in Figure below.

The key performance aspect of this system is in the three interfaces:

  1. Camera ⇔FPGA
  2. FPGA ⇔ PC/Hard disk drive (HDD)
  3. FPGA ⇔ RAM

If we consider the basic camera performance criteria, we have four issues to consider:

  1. Resolution
  2. Frame rate
  3. Color specification
  4. Clip size

In this example, the resolution is defined as being 640×480 pixels, the color mode is 24-bit color (3×8 bit planes), the maximum frame rate is 100 s and finally the basic clip size is anything up to 10 s.

What is not shown in the overview figure above is the requirement for some basic control options (such as ‘play’, ‘record’, ‘store’) to allow the stored clips to be replayed using a standard Video Graphics Array (VGA) output (available on most FPGA development kits) or stored for long-term storage on an HDD (or similar high-capacity storage device). This could be handled separately using a PC interface, but that detail is beyond the scope of this basic system description.

[For more information download this article from this site]