Floating-point systems were developed to provide high resolution over a large dynamic range. Floating-point systems can often provide a solution when fixed-point systems, with their limited dynamic range, fail. Floating-point systems, however, bring a speed and complexity penalty. Most microprocessor floating-point systems comply with the published single- or double-precision IEEE floating-point standard; while in FPGA-based systems often employ custom formats. In this research, a 16-bit floating-point unit, which has addition, subtraction, multiplication and division operator, and based on floating-point system, has been implemented in Altera FLEX10K FPGA using VHDL (VHSIC Hardware Description Language). The design used structural and behavior model implementation to know which the best design is. The best results are structural model using ROM which require 438 logic elements with 7.99 MFLOPS (million floating-point operations per second), and the behavior model using ROM which require 526 logic elements with 7.51 MFLOPS. The floating-point unit has been designed for normal floating-point operation, thus it can not detect overflow or underflow conditions.
Download full paper here (PDF) – The 1st International Seminar on Sciences and Technology (ISSTEC) 2009.