Technical Implementation of Dual Mode Fault Tolerance

Abstract

Field Programmable Gate Array (FPGA) is susceptible from hazardous radiation that leads to be in error state. In order to avoid that condition, we apply a fault tolerance technique. Most of the fault tolerances today are only using one mode, mean the fault tolerance that is applied will run all of the time without any changing its design. It is neglect about the condition, when the hazard radiation will occur more frequently or not. As researches have shown that in the orbit, the radiation hazard, which is happening frequently in the South Atlantic Anomaly (SAA). Therefore, in this project creates a new methodology in implementation of fault tolerance by using dual mode, when radiation is happened frequent we apply more robust fault tolerance, if not frequent we apply by simple fault tolerance. A robust fault tolerance will use more resources and simple fault tolerance will use less resources. Configuration in FPGA is done by Dynamic Partial Reconfiguration (DPR) means the transition from robust to simple fault tolerance or vice versa is done while the system is running. In this paper will talk about the technical implementation of dual mode fault tolerance, by presenting systematically order and important aspect to get success in implementing the design. The paper shows a result that dual mode fault tolerance can be configured in FPGA successfully.

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Tags: dynamic partial reconfiguration, Fault Tolerance, FPGA